1. Field of the Invention
The present invention generally relates to semiconductor processes, and more particularly to a method of fabricating an interconnect structure having reduced internal stress.
2. Description of the Prior Art
Low-resistance metals such as copper in conjunction with materials with low dielectric constants (“low-k dielectrics”) have been used to cope with parasitic capacitance and resistance effects resulting from adjacent interconnect structures fabricated in an integrated circuit chip. As known in the art, circuit performance in the deep submicron regime is increasingly a function of the delay time of electronic signals traveling between the millions of gates and transistors present on the integrated circuit chip.
Typically, interconnect structures formed on an integrated circuit chip consists of at least about 2 to 8 wiring levels. FIG. 1 to FIG. 3 are cross-sectional schematic diagrams illustrating a conventional single damascene process. As shown in FIG. 1, a lower damascened interconnect 110 is fabricated in a dielectric layer 10. Typically, the lower damascened interconnect 110 consists of a barrier 114 and a copper core 112. After chemical mechanical polishing, a dielectric barrier film 12 such as silicon nitride is deposited over the damascened interconnect 110 and over dielectric layer 10.
As shown in FIG. 2, a chemical vapor deposition (CVD) process is carried out to deposit a low-k dielectric film 14 onto the dielectric barrier film 12. The low-k film deposition process is terminated upon the desired film thickness, for example, 0.45 microns or 0.8 microns, is reached (i.e., one-step deposition). Thereafter, the low-k dielectric film 14 is subjected to a cooling or quenching process in the same CVD reactor (not shown) without breaking the vacuum thereof. After this, another dielectric barrier film 16 such as silicon nitride is deposited over the low-k dielectric film 14. The dielectric barrier film 16, the low-k dielectric film 14, and the dielectric barrier film 12 constitute a sandwich stack 20.
As shown in FIG. 3, a conventional lithographic process and a dry etching process are carried out to form a recessed trench in the sandwich stack 20. The recessed trench is situated directly above the lower damascened interconnect 110 and exposes a portion of the copper core 112. A barrier layer 124 and a copper layer 122 are then deposited in the recessed trench and then chemical mechanical polished to form the single damascene structure 120.
However, reliability problems are associated with the above-described prior art structure. For example, such structure is not sufficient to withstand present processing operations including the thermal cycling associated with semiconductor manufacturing. Ordinarily, the semiconductor device is subjected to about 5 to 20 thermal cycles to a temperature of 400–450° C. during manufacture. Also, during operation in the field, the device is further subjected to a large number of thermal cycles to a temperature of about 150° C. The reliability testing of completed IC's commonly includes a “thermal cycle” test in which the part is cycled hundreds of times between a selected low temperature and a selected high temperature.
One problem associated with the above-described structure is poor adhesion observed at the location of the interface of the upper wire level and bottom wire level. Poor adhesion is due to the high stress level of the material in the layers associated with the interface. This phenomenon is known as peeling. The details of this adhesion problem are not yet sufficiently clear or complete to those skilled in the art. It is believed that the problem of poor adhesion exists due to the high stress level of the material in the layers associated with the interface. Each material in these layers exhibits an internal stress, either tensile or compressive, which can eventually cause curving of the layer superimposed on another layer. By convention, tensile stress has a value greater than zero while compressive stress has a value less than zero. If the stress is particularly high so as to generate forces at the interface, which are greater than the adhesion forces between the layers, peeling occurs.
Therefore, it would be desirable to provide a method for making an interconnect structure that can provide better adhesion at the interface of the wire levels as well as a relatively low effective capacitance for the device. It would also be desirable for the interconnect structure to possess a substantially low stress level, i.e., one equal to about zero, thereby providing a stable structure when subjected to thermal cycles at both low temperatures, e.g., room temperature, and at high temperatures, e.g., temperatures above about 150° C.